technical data IW4019B quad and/or select gate high-voltage silicon-gate cmos ordering information IW4019Bn plastic IW4019Bdw soic t a = -55 to 125 c for all packages the IW4019B types consist of four and/or select gate configurations, each consisting of tw o 2-input and gates driving a single 2-input gate. selection is acco mplished by control bits s a and s b .in addition to selection of either channel a or channel b information, the control bits can be applied simultane ously to accomplish the logical a + b function ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package-temperature range; 100 na at 18 v and 25 c ? noise margin (over full p ackage temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply pin assignment logic diagram pin 16 =v cc pin 8 = gnd function table inputs outputs s a s b a b y h l h x h h l l x l l h x h h l h x l l l l x x l h h l l l h h l h h h h h l h h h h h h rev. 00
IW4019B rev. 00 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the reco mmended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard agains t damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage highe r than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
IW4019B rev. 00 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c 25 c 125 c unit v ih minimum high-level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low - level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 1 2 4 20 1 2 4 20 30 60 120 600 a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma
IW4019B ac electrical characteristics (c l =50pf, r l =200k , input t r =t f =20 ns) rev. 00 v cc guaranteed limit symbol parameter v -55 c 125 c unit 25 c maximum propagation delay, input a, b, s a or s b to output y (figure 1) 5.0 10 15 300 120 100 t plh , t phl 300 120 100 600 240 200 ns t tlh , t thl maximum output transition time, any output (figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance all a and b inputs - 7.5 pf s a and s b inputs - 15.0 pf figure 1. switching waveforms expanded logic diagram (1/4 of the device)
IW4019B n suffix plastic (ms - 001bb) dimensions, mm l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 16 8 9 symbol min max a 18.67 19.69 b 6.10 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 j 0 10 k 2.92 3.81 rev. 00 l 7.62 8.26 notes: m 0.20 0.36 1. imensions ?a?, ?b? do not include mold flash or protrusions. maximum mold flash or protrusions 0.25 mm (0.010) per side. n 0.38 d suffix soic (ms - 012ac) a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 16 8 9 dimensions, mm symbol . min max a 9.80 10.0 b 3.80 4.00 c 1.35 1.75 d 0.33 0.51 f 0.40 1.27 g 1.27 h 5.72 j 0 8 k 0.10 0.25 notes: m 0.19 0.25 1.dimensions a and b do not include mold flash or protrusion. p 5.80 6.20 2.maximum mold flash or protrusion 0.15 mm (0.006) per side for a, for b - 0.25 mm (0.010) per side. r 0.25 0.50
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